ADP2105/ADP2106/ADP2107
EVALUATION BOARD
EVALUATION BOARD SCHEMATIC FOR ADP2107 (1.8 V)
Data Sheet
VCC
OUT
C7
0.1μF
R3
10?
VCC
INPUT VOLTAGE = 2.7V TO 5.5V
VIN
C1
10μF 1
GND
J1
U1
16
15
14
13
FB
GND IN
PWIN1
EN
1
EN
LX2 12
R2
100k?
2
3
GND
GND
PGND 11
ADP2107-1.8
LX1 10
1
L1 2
2μH
2
OUTPUT VOLTAGE = 1.8V, 2A
V OUT
4
GND
PWIN2 9
VCC
OUT
R4
0?
C3
22μF 1
C4
22μF 1
COMP SS AGND PADDLE NC
5 6 7 8
C2
10μF 1
GND
R5
NS
R1
140k?
C6
68pF
C5
1nF
NC = NO CONNECT
1 MURATA X5R 0805
10μF: GRM21BR61A106KE19L
22μF: GRM21BR60J226ME39L
2 2μH INDUCTOR D62LCB TOKO
Figure 53. Evaluation Board Schematic of the ADP2107-1.8 (Bold Traces are High Current Paths)
RECOMMENDED PCB LAYOUT (EVALUATION BOARD LAYOUT)
JUMPER TO ENABLE
ENABLE
100kΩ PULL-DOWN
V IN
INPUT
GROUND
GROUND
INPUT CAPACITOR
PLACE THE FEEDBACK RESISTORS AS
CLOSE TO THE FB PIN AS POSSIBLE.
POWER GROUND
PLANE
CONNECT THE GROUND RETURN OF
ALL POWER COMPONENTS SUCH AS
INPUT AND OUTPUT CAPACITORS TO
THE POWER GROUND PLANE.
OUTPUT CAPACITOR
R TOP R BOT
C IN
C OUT
LX
OUTPUT
ADP2105/ADP2106/ADP2107
R COMP
C COMP
PLACE THE COMPENSATION
C SS
PGND
LX
C IN
INDUCTOR (L)
C OUT
OUTPUT CAPACITOR
V OUT
COMPONENTS AS CLOSE TO
THE COMP PIN AS POSSIBLE.
ANALOG GROUND PLANE
CONNECT THE GROUND RETURN OF ALL
SENSITIVE ANALOG CIRCUITRY SUCH AS
COMPENSATION AND OUTPUT VOLTAGE
DIVIDER TO THE ANALOG GROUND PLANE.
POWER GROUND
INPUT CAPACITOR
Figure 54. Recommended Layout of Top Layer of ADP2105/ADP2106/ADP2107
Rev. D | Page 28 of 36
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